Predicate Abstraction with Indexed Predicates

Predicate abstraction provides a powerful tool for verifying properties of infinite-state systems using a combination of a decision procedure for a subset of first-order logic and symbolic methods originally developed for finite-state model checking. We consider models containing first-order state variables, where the system state includes mutable functions and predicates. Such a model can describe systems containing arbitrarily large memories, buffers, and arrays of identical processes. We describe a form of predicate abstraction that constructs a formula over a set of universally quantified variables to describe invariant properties of the first-order state variables. We provide a formal justification of the soundness of our approach and describe how it has been used to verify several hardware and software designs, including a directory-based cache coherence protocol.Comment: 27 pages, 4 figures, 1 table, short version appeared in International Conference on Verification, Model Checking and Abstract Interpretation (VMCAI'04), LNCS 2937, pages = 267--28

Notes on "Bounds on BDD-Based Bucket Elimination''

This paper concerns Boolean satisfiability (SAT) solvers based on Ordered Binary Decision Diagrams (BDDs), especially those that can generate proofs of unsatisfiability. Mengel (arXiv:2306.00886) has presented a theoretical analysis that a BDD-based SAT solver can generate a proof of unsatisfiability for the pigeonhole problem (PHP$_n$) in polynomial time, even when the problem is encoded in the standard ``direct'' form. His approach is based on bucket elimination, using different orderings for the variables in the BDDs than in the buckets. We show experimentally that these proofs scale as $O(n^5)$. We also confirm the exponential scaling that occurs when the same variable ordering is used for the BDDs as for the buckets.Comment: Unpublished not

Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic

The logic of equality with uninterpreted functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic. By reducing formulas in this logic to propositional formulas, we can apply Boolean methods such as Ordered Binary Decision Diagrams (BDDs) and Boolean satisfiability checkers to perform the verification. We can exploit characteristics of the formulas describing the verification conditions to greatly simplify the propositional formulas generated. In particular, we exploit the property that many equations appear only in positive form. We can therefore reduce the set of interpretations of the function symbols that must be considered to prove that a formula is universally valid to those that are ``maximally diverse.'' We present experimental results demonstrating the efficiency of this approach when verifying pipelined processors using the method proposed by Burch and Dill.Comment: 46 page

Proof Generation for CDCL Solvers Using Gauss-Jordan Elimination

Traditional Boolean satisfiability (SAT) solvers based on the conflict-driven clause-learning (CDCL) framework fare poorly on formulas involving large numbers of parity constraints. The CryptoMiniSat solver augments CDCL with Gauss-Jordan elimination to greatly improve performance on these formulas. Integrating the TBUDDY proof-generating BDD library into CryptoMiniSat enables it to generate unsatisfiability proofs when using Gauss-Jordan elimination. These proofs are compatible with standard, clausal proof frameworks.Comment: Presented at 2022 Workshop on the Pragmatics of SA

Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator

This paper presents measurements obtained while performing fault simulations of MOS circuits modeled at the switch level. In this model the transistor structure of the circuit is represented explicitly as a network of charge storage nodes connected by bidirectional transistor switches. Since the logic model of the simulator closely matches the actual structure of MOS circuits, such faults as stuck-open and closed transistors as well as short and open-circuited wires can be simulated. By using concurrent simulation techniques, we obtain a performance level comparable to fault simulators using logic gate models. Our measurements indicate that fault simulation times grow as the product of the circuit size and number of patterns, assuming the number of faults to be simulated is proportional to the circuit size. However, fault simulation times depend strongly on the rate at which the test patterns detect the faults

Concurrent fault simulation of MOS digital circuits

The concurrent fault simulation technique is widely used to analyse the behavior of digital circuits in the presence of faults. We show how this technique can be applied to metal-oxide-semiconductor (MOS) digital circuits when modeled at the switch-level as a set of charge storage nodes connected by bidirectional transistor switches. The algorithm we present is capable of analysing the behavior of a wide variety of MOS circuit failures, such as stuck-at-zero or stuck-at-one nodes, stuck-open or stuck-closed transistors, or resistive opens or shorts. We have implemented a fault simulator FMOSSIM based on this algorithm. The capabilities and the peformance of this program demonstrate the advantages of combining switch-level and concurrent simulation techniques

Switch-Level Modeling of MOS Digital Circuits

The switch-level model describes the logical behavior of digital circuits implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X, and each transistor having a state open, closed, or unknown. The logic simulator MOSSIM II has been implemented with this model as its basis. MOSSIM II can simulate a wide variety of MOS circuits at speeds approaching those of event-driven logic gate simulators. The simulator can apply additional tests to detect potential timing errors, unrestored logic levels in CMOS, and unrefreshed dynamic charge. This paper provides an overview of the switch-level model and how it is applied in MOSSIM II

Switch-Level Model and Simulator for MOS Digital Systems

The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open", "closed", or "indeterminate". Many characteristics of 140S circuits can be modeled accurately, including: ratioed, complementary, and precharged logic-, dynamic and static storage; (bidirectional) pass transistors; busses; charge sharing; and sneak pa ths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and has been used to simulate circuits containing over 10,000 transistors. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS

Generating Extended Resolution Proofs with a BDD-Based SAT Solver

In 2006, Biere, Jussila, and Sinz made the key observation that the underlying logic behind algorithms for constructing Reduced, Ordered Binary Decision Diagrams (BDDs) can be encoded as steps in a proof in the extended resolution logical framework. Through this, a BDD-based Boolean satisfiability (SAT) solver can generate a checkable proof of unsatisfiability for a set of clauses. Such a proof indicates that the formula is truly unsatisfiable without requiring the user to trust the BDD package or the SAT solver built on top of it. We extend their work to enable arbitrary existential quantification of the formula variables, a critical capability for BDD-based SAT solvers. We demonstrate the utility of this approach by applying a prototype solver to several problems that are very challenging for search-based SAT solvers, obtaining polynomially sized proofs on benchmarks for parity formulas, as well as the Urquhart, mutilated chessboard, and pigeonhole problems.Comment: Extended version of paper published at TACAS 202